1. Field of the invention
The present invention relates to a semiconductor device, and particularly to protection techniques for a circuit for driving a power MOSFET functioning as a switch.
2. Description of Related Art
In recent years, a relay used for a unit in automobile electric equipment has been replaced with a semiconductor device such as a power MOSFET for contactless switching. Also, an intelligent power device (IPD) has been used that includes protective functions such as a current limiting circuit, an overheat sensing circuit and a wire break sensing circuit for the power MOSFET, and is capable of transferring the result of self-diagnosis to a control microprocessor.
In such IPD, when a break of a grounding wire of the IPD occurs (ground float), an output of the IPD will be turned on, though desired to be turned off, and thereby the IPD itself may be damaged. Then, it is required for the IPD to include a break sensing function as one of the protective functions. For example, Japanese Patent Laid-Open No. 3-166816 discloses a semiconductor integrated circuit device which protects its element from being damaged due to a break of a grounding wire. This semiconductor integrated circuit device includes a grounding wire break detection circuit for detecting whether or not electrical current flows through a grounding wire, and a switch element for forcibly turning off a power output element according to a wire break detection output signal supplied from the grounding wire break detection circuit. According to such semiconductor integrated circuit device, because the power output element is forced to be turned off when a break of a grounding wire or a poor electrical contact occurs in an IC, an element can be protected from generating heat and being destroyed by the heat
FIG. 4 is a circuit diagram of the semiconductor integrated circuit device shown in Japanese Patent Laid-Open No. 3-166816. In FIG. 4, when an input terminal IN connected to an input port of an inverter circuit N1 becomes a high level, a gate potential of a MOSFET Q2 connected to an output port of the inverter circuit N1 becomes a low level. The MOSFET Q2, then, is brought into an off state, and an output voltage of a booster circuit BST is supplied to a gate of a power MOSFET Q1 to turn on the power MOSFET Q1. On the one hand, when the input terminal IN becomes a low level, the MOSFET Q2 is turned on, and the power MOSFET Q1 is turned off because the gate is separated from the output voltage of the booster circuit BST.
A grounding wire break detection circuit, here, includes a current mirror circuit composed of transistors T1 and T2, and a resistor R1. When a GND terminal is normally connected to an external ground potential, bias current flows in the current mirror circuit. In this case, the transistor T2 is brought into an on state, and a collector potential of the transistor T2 becomes a low level. Accordingly, a MOSFET Q3 is turned off, and the gate of the power MOSFET Q1 will not be affected.
On the other hand, when the GND terminal is in a wire break state, electric current does not flow through a current path formed of the resistor R1 and the transistor T1, and the transistor T2 is turned off. Accordingly, a power supply VDD provides a gate potential of the MOSFET Q3 through a transistor T3 and a resistor R2, and the gate potential rises. Accordingly, the MOSFET Q3 is brought into an on state, and the MOSFET Q1 is forced to be turned off. Accordingly, heat generated by electric current flowing through the MOSFET Q1 and element destruction caused by the heat can be prevented.
In addition, Japanese Patent Laid-Open No. 5-6966 discloses an electric circuit device, as the related art, which can normally operate even when a terminal of one internal circuit to be connected to a predetermined, external potential, for example, a grounding terminal, is disconnected to become open, and report outside that the grounding terminal is brought into the open state.
By the way, in a semiconductor integrated circuit device (semiconductor device), for example, as shown in FIG. 5, a P-type diffusion layer is formed on an N-type substrate connected to a power supply terminal Vcc, and an integrated circuit is formed thereon. The P-type diffusion layer, then, is connected to a grounding terminal GND. In such semiconductor integrated circuit device configured as described above, there is a parasitic capacitance Cj between the N-type substrate and the P-type diffusion layer, generated by a pn-junction reversely biased.
FIG. 6 schematically shows the presence of a parasitic capacitance in a semiconductor device working as the IPD. In FIG. 6, the semiconductor device, which is the IPD, is supplied with power (for example, 14V) by a power supply such as a battery to a power supply terminal Vcc, and supplies a load with power through an output terminal OUT. The semiconductor device functions as a switch for determining whether or not power is supplied to the load, based on an active signal selectively applied to an input terminal IN. There is, as shown in FIG. 5, a parasitic capacitance Cj between an internal GND (an internal grounding wire) to be connected to a grounding terminal GND of such semiconductor device and the power supply terminal Vcc.
The present inventor has recognized that, in such semiconductor device, a damage of an output MOS transistor caused by a GND wire break may often stem from a half-on state of the output MOS transistor produced at power-on by a parasitic capacitance Cj between Vcc and GND (the half-on state is that a transistor is not completely turned on, and has a potential between a drain and a source).
FIG. 7 shows an example of change in inrush current Id generated by a parasitic capacitance of a semiconductor device. FIG. 7 shows that the inrush current Id goes up to 2 to 4 (A) when the parasitic capacitance Cj (CVCC−GND) is 50, 75 and 100 pF.
By the way, the semiconductor integrated circuit device described in Japanese Patent Laid-Open No. 3-166816 detects whether or not electric current flows through a grounding wire. That is, when electric current is made to flow full-time in a grounding wire break detection circuit for detecting whether or not the electric current flows through the grounding wire, a grounding wire break is determined based on detecting no electric current flowing through the grounding wire.
When power is applied to such semiconductor integrated circuit device, with the grounding wire being broken, then a collector of the transistor T2 is charged up through a transistor T3 and a resistor R2 shown in FIG. 4, and the MOSFET Q3 is turned on. At this time, to control circuit current to be lower, a resistor having a satisfactorily large value has to be used for the resistor R2. Accordingly, a collector potential of the transistor T2 rises slowly, resulting in a late timing to forcibly turn off the MOSFET Q1, so that the MOSFET Q1 may be damaged. Especially, the late detection at power-on is more likely to cause a crucial damage.